In a semiconductor test process, a conductivity test is sometimes performed to detect a defective product by bringing probes having conductivity (conductive probes) into contact with a semiconductor wafer before dicing (WLT: Wafer Level Test). When this WLT is performed, to transfer a signal for a test generated and sent by a testing device (tester) to the semiconductor wafer, a probe card including a large number of probes is used. In the WLT, the probes are individually brought into contact with each of dies on the semiconductor wafer while the dies are scanned by the probe card. However, because several hundreds to several ten thousands dies are formed on the semiconductor wafer, it takes considerable time to test one semiconductor wafer. Thus, an increase in the number of dies causes higher cost.
To solve the problems of the WLT, recently, a method called FWLT (Full Waver Level Test) is also used in which several hundreds to several ten thousands probes are collectively brought into contact with all or at least a quarter to a half of dies on a semiconductor wafer. To accurately bring the probes into contact with the semiconductor wafer, this method requires technologies for maintaining positional accuracy of tips of probes by accurately keeping the parallelism or the flatness of a probe card with respect to a predetermined reference surface and for highly accurately aligning a semiconductor wafer.
FIG. 17 is a schematic diagram of the structure of a main part of a probe card applied in the FWLT. A probe card 41 shown in the figure includes a plurality of probes 42 arranged in association with electrode pads 101 provided in a semiconductor wafer 100, a probe head 43 that houses the probes 42, and a space transformer 44 as a relay substrate that transforms a space of a fine wiring pattern in the probe head 43 and relays wires. In the space transformer 44, electrode pads 45 are provided in positions corresponding to the probes 42 housed in the probe head 43. Tips of the probes 42 are in contact with the electrode pads 45. Wires (not shown) having a pattern corresponding to the electrode pads 45 are provided in the space transformer 44. The wires are connected to a substrate for a test via an interposer (the interposer and the substrate are not shown).
Patent Document 1: Japanese Patent Application Laid-open No. 2003-240801